PE64905
Product Specification
Table 1. Electrical Specifications @ 25°C, V DD = 2.6V
Parameter
Operating Frequency Range
Minimum Capacitance
Maximum Capacitance
Parasitic Capacitance
Configuration
Both
Series
Shunt
Series
Shunt
Series
Condition
State = 00000, 100 MHz (RF+ to RF-)
State = 00000, 100 MHz (RF+ to Grounded RF-)
State = 11111, 100 MHz (RF+ to RF-)
State = 11111, 100 MHz (RF+ to Grounded RF-)
All States, 100 MHz (RF+ to GND, RF- to GND)
Min
100
0.49
0.99
4.09
4.59
Typ
0.60
1.10
4.60
5.10
0.5
Max
3000
0.71
1.21
5.11
5.61
Units
MHz
pF
pF
pF
Tuning Ratio
Series
Shunt
100 MHz
100 MHz
7.7:1
4.6:1
Quality Factor (C min )
Quality Factor (C max )
Harmonics (3fo)
Step Size
Equivalent Series Resistance
1
1
Self Resonant Frequency
Harmonics (2fo) 2
2
Input Intercept Point (2nd Order)
Input Intercept Point (3rd Order)
Switching Time 3, 4
Start-up Time 3
Wake-up Time 3, 4
Both
Series
Shunt
Shunt
Shunt
Series
Series
Series
Both
Both
Both
5 bits (32 states), constant step size (100 MHz)
State = 00000
State = 11111
100 MHz, with L s removed
1 GHz, with L s removed
2 GHz, with L s removed
3 GHz, with L s removed
100 MHz, with L s removed
1 GHz, with L s removed
2 GHz, with L s removed
3 GHz, with L s removed
State 00000
State 11111
100 MHz - 3 GHz
100 MHz - 3 GHz
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
100 MHz - 3 GHz, +18 dBm per tone, 1 MHz Spacing
50% CTRL to 10/90% delta capacitance between any two
states
Time from V DD within specification to all performances within
specification
State change from standby mode to RF state to all perfor-
mances within specification
0.129
1.40
1.33
10
35
32
25
27
25
11
6
7.5
3.1
105
65
-36
-36
12
100
100
pF
?
GHz
dBm
dBm
dBm
dBm
μs
μs
μs
Notes: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit.
Q = X C /R = (X-X L )/R, where X = X L +X C , X L = 2*pi*f*L, X C = -1/(2*pi*f*C), which is equal to removing the effect of parasitic inductance L S.
2. In series or shunt between 50 ? ports. Pulsed RF input with 4620 μs period, 50% duty cycle, measured per 3GPP TS 45.005.
3. DC path to ground at RF+ and RF- must be provided to achieve specified performance.
4. State change activated on rising edge of SCL for ACK bit following data word.
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0335-06
│ UltraCMOS ? RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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